- Reference flow featuring the Cadence Integrity 3D-IC Platform is enabled for die-on-die 3D-IC stacking
- Ongoing collaboration focuses on providing customers with optimal TSV placement in stacked die designs
- Users can devise an optimal 3D structure placement on a die, reducing area and wirelength penalties, while optimizing PPA for each die
Cadence Design Systems, Inc. (Nasdaq: CDNS), a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE™), today announced that it has expanded its collaboration with Samsung Foundry to accelerate 3D-IC design. Through the continued collaboration, the reference flow featuring the Cadence® Integrity™ 3D-IC platform has been enabled to advance Samsung Foundry’s 3D-IC methodology. Using the Cadence platform, customers creating complex, next-generation hyperscale computing, mobile, automotive and AI applications can greatly optimize power, performance and area (PPA) for each die.
The PPA of a design can be impacted when chips are stacked in a 3D-IC configuration versus a 2D configuration due to the presence of large 3D structures like TSVs, which connect the stacked chips. In addition to blocking standard cell placement area, these structures block routing resources as well. The Cadence Integrity 3D-IC platform alleviates these traditional challenges, letting users create multiple TSV insertion scenarios and devise an optimal 3D structure placement on a die with reduced wirelength penalties while boosting PPA and productivity. The platform also lets users perform 3D-IC design planning, implementation and signoff from a single cockpit, making the design process faster and easier.
“Customers creating stacked die designs at advanced nodes are always looking to make use of the benefits of our technologies without compromising PPA,” said SangYun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “The enablement that resulted from our collaboration with Cadence leverages advanced 3D-IC capabilities that provide our mutual customers with innovative techniques to build 3D designs without giving up PPA due to the additional structures introduced with multi-die stacking. After working with Cadence successfully on the 3D-IC system planning reference flow, we are confident our customers can achieve their own unique design goals for multi-die stacked designs.”
“Through our latest collaboration with Samsung Foundry, we’re enabling customers to circumvent the typical challenges that arise with 3D-IC design while optimizing PPA in parallel,” said Vivek Mishra, corporate vice president of the Digital and Signoff Group at Cadence. “The Integrity 3D-IC platform brings together leading silicon and package implementation with system analysis capabilities, helping designers improve overall productivity. By leveraging Samsung Foundry’s advanced 3D-IC capabilities and the Integrity 3D-IC platform, our customers have access to an optimal solution for high-quality, multi-die implementation.”
The Integrity 3D-IC platform supports the company’s Intelligent System Design™ strategy, enabling SoC design excellence. For more information on the Integrity 3D-IC platform, please visit www.cadence.com/go/integrityands.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
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Cadence, a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE), today announced that it has expanded its collaboration with Samsung Foundry to accelerate 3D-IC design.