- Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure
- Early customers seeing more than 2.5X design cycle reduction on common analog blocks
- Cadence Virtuoso design platform is optimized for design migration and automation of TSMC FinFET technologies
Cadence Design Systems, Inc. (Nasdaq: CDNS) collaborated with TSMC to develop a node-to-node design migration flow built upon the Cadence® Virtuoso® design platform for custom/analog IC blocks that use TSMC’s advanced process technologies. The Cadence and TSMC R&D teams worked together to ensure the Virtuoso Schematic Editor and Layout Editor automatically migrate a source design on TSMC N5 and N4 process technologies to a new design on TSMC N3E process technology. Early analog design IP trials of the new migration flow showed that design time on common analog blocks was more than 2.5X faster compared with manual migration.
The Virtuoso Application Library Environment schematic migration solution, which is integrated into the Virtuoso design platform, automatically migrates a source schematic’s cells, parameters, pins and wiring from one process node to another technology. The target schematic is then tuned and optimized using the Virtuoso ADE Product Suite’s simulation environment and circuit optimization technology to verify the new schematic meets all necessary measurement targets.
The Virtuoso Layout Suite supports the reuse of existing layouts on a given process technology to quickly recreate a migrated layout on a new process technology, using custom place and route automation. Thanks to Virtuoso Layout Suite templates, TSMC’s analog-mapping technology and the routing technology in the Virtuoso design platform, designers can automatically recognize and extract groups of devices in an existing layout and apply templates to similar groups in the new layout.
“Through our continued collaboration with Cadence, we’re enabling our customers to improve productivity and accelerate design closure when performing node-to-node design migration of analog blocks within the Virtuoso design platform,” said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. “Through the availability of our enhanced PDKs, we’re making it easy for our customers to easily migrate custom/analog blocks from one of our widely used processes to another and benefit from the power, performance, and area improvements of our latest technologies.”
“By working closely with TSMC, our customers now have access to the most sophisticated migration and custom/analog place and route automation capabilities within the Virtuoso design platform,” said Tom Beckley, senior vice president and general manager in the Custom IC, IC Packaging, PCB and System Analysis Group. “We’ve continuously collaborated with our mutual customers to understand their real-world design requirements. This new easy-to-use, node-to-node design migration technology addresses a key requirement for our customers’ most challenging custom analog designs.”
The Cadence Virtuoso design platform supports the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence. For more information on the Virtuoso design platform, please visit http://www.cadence.com/go/virtuosomigrationpr.
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